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page 1 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 features two receivers and one transmitter harris/holt/raytheon pin for pin replacement wraparound self - test mode word length of 25 or 32 bits parity status and generation of receive and transmit words 8 word transmitter buffer low power cmos processing su pports multiple arinc data busses: 429, 571, 575, 706. dei 1016 arinc 429 transceiver device engineering incorporated g eneral description: the dei 1016 provides an interface between a standard avionics type serial digital data bus and a 16 - bit - wid e digital data bus. the interface circuit consists of a single channel transmitter with an 8x32 bit buffer, two ind e- pendent receive channels, and a host programmable control register to select operating options. the two r e- ceiver channels operate identically, each providing a direct electrical interface to an arinc data bus. the transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data into the transmitter. the block of data is transmitted automatically by enabling the tran s- mi t ter with no further attention by the host computer. data is transmitted in ttl format on the d0(a)/d0(b) ou t- put pins. the signal format is compatible with dei?s extensive line of arinc 429 line drivers for easy conne c- tion to the arinc data bus. 430 s. rockford dr. tempe, az 85281 phone: (480) 303 - 0822 fax: (480) 303 - 0824 e - mail: info@deiaz.com figure 1: DEI1016 block diagram control register tx fifo 8 words x 32 bits 16 bit receive decoder receive decoder transmit encoder arinc 429 receive 0 arinc 429 receive 1 self test data arinc 429 transmit data bus host interface 32 bit 32 bit 32 bit 16 bit 32 bit /dr1or/dr2 txr /oe1 or /oe2 /ld1 or /ld2 entx /ldcw /dbcen /mr
page 2 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 table 1: dei 1016 absolute maximum ratings parameter symbol min max units supply voltage v dd - 0.5 +7.0 v dc input voltage (except pins di1(a,b) and di2(a,b)) v in - 0.3 v cc + 0.3 v voltage at pins di1(a,b) and di2(a,b) v in - 29 +29 v dc output current per pin - 25 +25 ma dcv or gnd current per pin - 50 +50 ma storage temperature t stg - 65 +150 c operating temperature t o - 55 +125 c 1mck clock frequency 1.16 mhz table 2: dei 1016 dc electrical characteristics unless noted, operating connections: v dd = 5v 10%, t = - 40oc ~ +85oc parameter symbol conditions min typ max units arinc line inputs logic 1 input voltage v ih v diff di(a) and di(b) 6.5 10 13 v logic 0 input voltage v il v diff di(a) and di(b) - 6.5 - 10 - 13 v null input voltage v nul v diff di(a) and di(b) - 2.5 0 +2.5 v common mode voltage v cm 5 v differential input impedance r i 12 k w input impedance to v dd r h 12 k w input impedance to gnd r g 12 k w differential input capacitance c i 20 pf input capacitance to v dd c h 20 pf input capacitance to gnd c g 20 pf all other inputs (including bi - directional) max low level input voltage v il 0.8 v min high level input voltage v ih 2 v max input current i in v in = gnd to v dd 10 m a input capacitance c in 15 pf all outputs (including bi - directional) min high level output voltage v oh i oh = 20 m a (cmos) i oh = 6ma (ttl) v dd ? 0.1 2.7 v max low level output voltage v ol i ol = 20 m a (cmos) i ol = 6ma (ttl) 0.1 0.4 v supply current i dd 1mck = 1mhz 5 10 ma supply voltage v dd 4.5 5 5.5 vdc power supply input
page 3 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 table 4: pin definitions symbol definition v dd +5vdc 10 %; power supply di1(a) data in 1, hi ( input, arinc 429 compatible ) arinc 429 ?a? data input to receiver 1. di1(b) data in 1, lo ( input, arinc 429 compatible ) arinc 429 ?b? data input to receiver 1. di2(a) data in 2, hi ( input, arinc 429 compatible ) arinc 429 ?a? data input to receiver 2. di2(b) data in 2, lo ( input, arinc 429 compatible ) arinc 429 ?b? data input to receiver 2. /dr1 data ready receiver 1. (output, active low) logic ?0? indicates valid data in receiver 1. /dr2 data ready receiver 2. (output, active low) logic ?0? indicates valid data in receiver 2. sel receiver data select. selects receiver word 1 or 2 to be read by the data bus. /oe1 receiver 1 data enable. (input, active low). logic ?0? enables selected data from receiver 1 on to the data bus. /oe2 receiver 2 data enable. (input, active low). logic ?0? enables selected data from receiver 2 on to the data bus. d0 - d15 16 - bit data bus (bi - directional, tri - state) bi - directional data bus for reading data from either receivers, or for writing data into the transmitter memory or control register. /ld1 load transmitter word 1 (input, active low) logic ?0? pulse loads word 1 into the transmitter memory from data bus. /ld2 load transmitter word 2 (input, active low) logic ?0? pulse loads word 2 into the transmitter memory from data bus. txr transmitter ready (output, active high) logic ?1? indicates the transmitter memory is empty and ready to accept new data. do(a) transmitter data, hi (output, active high, return to zero) logic ?1? indicates transmitter data bit is a 1. the signal returns to zero for second half of bit time. do(b) transmitter data, lo (output, active high, return to zero) logic ?1? indicates transmitter data bit is a ?0?. the signal return s to zero for second half of bit time. entx enable transmitter (input, active high) logic ?1? enables transmitter to send data from transmitter me m- ory. this must be logic ?0? while writing data into transmitter memory. transmitter memory is cleared by high - to - low transitio n. /ldcw load control register (input, active low) logic ?0? pulse loads control register from the data bus. 1mck external clock (input, ttl compatible) master clock used by both the receivers and transmitter. the 1mhz rate is a x10 clock fo r the hi data rate (100 kbps), and a x80 clock for lo data rate (12.5 kbps) txck transmitter clock (output) delivers a clock frequency equal to the transmit data rate. the clock is a l- ways enabled and in phase with the data. the clock is a logic ?1? during the first half of the data bit time. /mr master reset (input, active low pulse) logic ?0? resets transmitter memory, bit counters, word counter, gap timers, /drx, and t xr. used on power up and system reset. /dbcen data bit control enable (input, active low with internal pull up to v dd ) logic ?0? enables the transmitter parity bit control f unction as defined by control register bit 4 (paren). logic ?1? forces transmitter parity bit insertion regardless of paren valu e. pin is normally left open or tied to ground. table 3: dei 1016 ac electrical characteristics parameter symbol data rate 100kbps data rate 12.5kbps min max min max units 1mck duty cycle ck dc 40 60 40 60 % 1mck rise/fall time t crf 10 10 ns master reset pulse width t mr 200 200 ns transmitter data rate (1mck = 1mhz) t dr 99 101 12.4 12.6 kbps receiver data rate (1mck = 1mhz) r dr 95 105 9.0 14.5 kbps 1mck frequency f 1mck 1.01 1.01 mhz
page 4 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 functional description: the dei 1016 supports a number of various options which are selected by data written into the control re gister. data is written into the control register from the 16 - bit data bus when the /ldcw signal is pulsed to a logic ?0?. the twelve control bits control the following functions: 1) word length (32 or 25 bits) 2) transmitter bit 32 (parity or data) 3) wrap around self test. 4) source destination code checking of received data. 5) transmitter parity (even or odd) 6) transmi tter and receiver data rate (100 or 12.5 kbps) table 6: dei 1016 control word name data bit description paren d4 transmitter parity enable. enables parity bit insertion into transmitter data bit 32. parity is always inserted if /dbcen is o pen or hi. if /dbcen is lo, logic ?0? on paren inserts data on bit 32, and logic ?1? on paren inserts parity on bit 32. /slftst 1 d5 self test enable. logic ?0? enables a ?wrap around? test mode which internally connects the transmitter outputs to both receive r inputs, bypassing the receiver front end. the test data is inverted before going into receiver 2 so that its data is the complement of that received by r e- ceiver 1. the transmitter output is active during test mode. sden1 2 d6 s/d code check enable for receiver 1. logic ?1? enables the source/destination decoder for receiver 1. x1, y1 2 d7, d8 s/d compare code rx1. if the receiver 1 s/d code check is enabled (sdenb1=1), then i n- co m ing receiver data s/d fields will be compared to x1, y1. if they match, the word will be accepted by receiver 1; if not, it wi ll be ignored. x1 (d7) is compared to serial data bit 9, y1 (d8) is compared to serial data bit 10. sden2 2 d9 s/d code check enable for receiver 1. logic ?1? enables the source/destination decoder for receiver 1. x2, y2 2 d10, d11 s/d compare code rx2. if the receiver 2 s/d code check is enabled (sdenb2=1), then i n- co m ing receiver data s/d fields will be compared to x2, y2. if they match, the word will be accepted by receiver 2; if not, it wi ll be ignored. x2 (d10) is compared to serial data bit 9, y2 (d11) is compared to serial data bit 10. parck d12 parity check enable. logic ?1? inverts the transmitter parity bit for test of parity circuits. logic ?0? selects normal odd pa rity; logic ?1? selects even parity. txsel 3 d13 transmitter data rate select. logic ?0? sets the transmitter to the hi data rate. hi rate is equal to the clock rate divided 1 0. logic ?1? sets the transmitter to the lo data rate. lo rate is equal to the clock rate divided by 80. rcvsel 4 d14 receiver data rate select. logic ?0? sets both receivers to accept the hi data rate. the nom i nal hi data rate is the input clock divided by 10. logic ?1? sets both receivers to the lo data rate. the nominal lo data rate is the input clock divided by 80. wlsel 5 d15 word length select. logic ?0? sets the transmitter and receivers to a 32 bit word format. logic ?1? sets them to a 25 bit word format. notes: 1)the test mode should always conclude with ten null?s. this step prevents both receivers from accepting invalid data. 2) sdenbn, xn & yn should be changed within 20 bit times after /drn goes low and the bit stream has been read, or within 30 bit times after a master reset has been removed. 3)txsel should only be changed during the time that txr is high or master reset is low. 4)rcvsel should be changed only during a master reset pulse. if changed at any other time, then the next bit stream from both receiver 1 and receiver 2 should be ignored. 5)when the control word is written the effect of the wlsel bit will take effect immediately on the first complete arinc word r e- ceived or transmitted following the control word write operation. not used d0 - d4 when writing to the control register, the four ?not used bits? are ?don?t care? bits. these four bits will not be used on the c hip. table 5: control register format bit symbol bit symbol d15 (msb) wlsel d7 x1 d14 rcvsel d6 sdenb1 d13 txsel d5 /slftst d12 parck d4 paren d11 y2 d3 not used d10 x2 d2 not used d9 sdenb2 d1 not used d8 y1 d0 not used
page 5 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 data format: the arinc serial data is shuffled and formatted into two 16 bit words (word1 and word2) used by the bi - directional data bus interface. figure 2 shows the mapping between the 32 bit arinc serial data and the two data words. figure 3 describes the mapping for the 25 bit serial word used when control register bit wlsel is set to logic ?1?. 29 26 27 28 1 2 3 4 32 31 30 22 19 20 21 25 24 23 15 12 13 14 18 17 16 8 5 6 7 11 10 9 1 2 3 4 15 12 13 14 0 8 5 6 7 11 10 9 1 2 3 4 15 12 13 14 0 8 5 6 7 11 10 9 parity ssm sign data msb lsb s/d or data label lsb msb sign data msb data lsb s/d or data ssm parity label lsb msb word 2 format word 1 format bit function bit function 32 bit arinc serial data format (bit 1 is transmitted first) figure 2: mapping of serial data to/from word 1 and word 2 in 32 bit format. 1 2 3 4 22 19 20 21 25 24 23 15 12 13 14 18 17 16 8 5 6 7 11 10 9 1 2 3 4 15 12 13 14 0 8 5 6 7 11 10 9 1 2 3 4 15 12 13 14 0 8 5 6 7 11 10 9 parity data msb lsb label lsb msb data msb not used parity label lsb msb word 2 format word 1 format bit function bit function 25 bit arinc serial data format (bit 1 is transmitted first) lsb figure 3: mapping of serial data to/from word 1 and word 2 in 25 bit format.
page 6 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 r eceiver operation: since the receivers function identically, only one will be discussed in detail. the receiver consists of the follo w- ing circuits. line receiver the front end of the line receiver functions as a vol t- age level translator. it transforms the 10 volt differe n- tial arinc data signals into 5 volt internal logic levels. the line receivers are protected against shorts to 29 volts and pro vides common mode voltage rejection. the outputs of the line receiver are one of two inputs to the self - test data selector. th e other input to the data selector is the self - test signal from the transmitter section. the self - test signals are inverted goi ng into receiver 2. the data selector is controled by control register bit d5 (slftst). self-test data selector slftst do(a) di1(a) di1(b) comparator to receive decoder figure 4: line receiver block diagram i ncoming data the incoming data (either self test or arinc) is triple sampled by the word gap timer to generate a data clock. th e start of each bit is first detected and then verified two receive - clock cycles later. the receive clock is 1mhz for hi speed and 125 khz for lo speed operation and is generated by the receiver/transmitter timing circuit. the receive clock is ten times the normal data rate to ensure no data ambiguity. data clock the derived data clock then shifts the data down a 32 bit long data shift register. the data word length is selectable for either 25 or 32 bits long by control regi s- ter bit wlsel. as soon as the data word is completely received, an internal signal is generated by the word gap timer circuit t o enable loading data into the 32 bit receive buffer latch. s/d decoder the source/destination decoder compares the user set cod e (x and y) with bits 9 and 10 of the data word. the decoder can be enabled and disabled by the sdenb bit of the control regist er. if the two codes are matched, a signal is generated to latch in the received data into the receiver buffer. otherwise the data word is ignored and not latched into the receive buffer. if the data is latched, the data ready flag (/drn) is set to indi cate to the user that a valid data word is ready to be read. parity control the parity of the incoming message is checked when either word of the receiver is read. logic ?0? indicates t he received word has an odd number of 1?s (no error). logic ?1? indicates the received word has an even nu m- ber of 1?s (error condition). if the data format has data in bit 32 instead of parity, the user software must calc u- late the value of the 32nd bit. if word 1 and word 2 together have an even number of 1?s, then data bit 32 is a logic ?1?. oth erwise, it is a logic ?0?. data access to access the receiver data, the user sets the receiver data select input (sel) to a logic ?0? and pulses the ou t- put enable (/oen) line with a logic ?0?. this causes data word 1 to be placed on the 16 bit data bus. to read word 2, the user sets the data select input (sel) to a logic ?1? and pulses the output enable (/oen) low to place word 2 on the data bus. when both word 1 and word 2 have been read, drn will be reset. this reset is triggered by the leading edge of the final /oen pulse. if a new data word is received before the previous data has been read from the receiver buffer (as indicated by the /drn signal flip - flop), the receive buffer will not be over written by the new data. the new data will remain in the shift register until either the /drn signal is reset and it can be written into the receive buffer or it is ove r- written by the next incoming data word. data in the shift register will be overwritten by new incoming data, while data that ha s been latched into the receive buffer can not be overwritten. data error conditions if the receiver input data word string is b roken before the entire data word is received, the receiver will reset and ignore the partially received data word. if the rece iver input data word string is not properly framed with at least 1 null bit before the word and 1 null bit after the word, the r eceiver will reset and ignore the improperly framed data word. transmitter operation: the transmitter section consists of an 8 word by 32 bit fifo, parity generator, transmitter word gap timer, and a ttl output circuit. fifo buffer the 8x32 buffer memory allows the user to load up to 8 words into the transmitter, enable it, and then ignore it while the transmitter ships out the data without further a t- te n tion. data is loaded into the buffer by pulsing /ld1 to load the first 16 bits (word 1) from the data bus, and pul s ing /ld2 to load word 2. /ld1 must always precede / ld2. the transmitter must always be disabled while loa d- ing the buffer (entx = logic "0"). if the buffer is full and new data is pulsed with /ld1 and / ld2, the last 32 bit word in the buffer will be overwritten. data will remain in the buffer until entx is pulsed to a logic ?1?, which will activate the fifo cl ock and data is shifted out serially to the transmitter driver.
page 7 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 f ifo buffer (continued) the buffer data is transmitted until the last word in the buffer is shifted out. at this time a transmit ter ready signal (txr) is set to a logic ?1? indicating that the buffer is empty and ready to receive up to eight more data word s. writing into the buffer memory is disabled when entx is set to logic ?1?. transmitter ready signal (txr) the transmitter rea dy flag (txr) is set to logic ?0? with the first occurrence of an /ld2 pulse to indicate that the buffer is not empty. output re gister the output register is designed such that it can shift out a word of 25 bits or 32 bits. the length is controlled by co n- trol register bit "wlsel". tx word gap timer the tx word gap timer circuit inserts a 4 bit time gap b e- tween words. this gives a minimum requirement of a 29 bit time or a 36 bit time for each word transmission. the 4 bit time gap i s also automatically maintained when the next new block of data is loaded into the buffer, which may take less than one bit time . parity generator the parity generator calculates either odd or even parity as specified by control register bit "parck". odd parity is no r- mally used; even parity is available to test the receiver pa r- ity check circuit. odd parity means that there is an odd number of 1's in the 25 or 32 bit serial word. bit 8 of word one is rep laced with a parity bit if parity is selected by the control register bit "paren" and the /dbcen pin. othe r- wise, bit 8 is passed through as data. transmitter output the transmitter driver outputs three ttl compatible si g- nals: 1) do(a), 2) do(b), and 3) txclk. do(a) and do (b) are the transmitter data in two rail, return - to - zero fo r- mat. do(a) indicates a logic "1" data bit by going to a "1" for the 1st half of a bit time, then returning to "0" for the 2nd ha lf; do(b) remains at "0" for the whole bit time. in the same fashion, do(b) indicates a logic "0" data bit by pulsing hi while do(a) remains lo. a null bit is indicated when both signals remain lo. it is illegal for both signals to be logic "1". the txclk is a free running clock signal of 50% duty cycle and in phase with transmitter data. the clock will always be logic "1" during the first half of a bit time. power - up reset an internall power - up reset circuit prevents erroneous data transmission before an external master reset has been a p- plied. 25 - bit word operation: the transceiver implements a 25 bit word format which may be used in non - arinc applications to en hance data transfer rate. the format is a simplified version of the 32 bit arinc word and is described in figure 3. it consists of an 8 bit label, a 16 bit data word, and a parity bit. the parity bit can optionally be replaced with a 17th data bit. the source/destination code checking option can be e n- abled in either receiver. it will operate on bits 9 and 10 of the 25 bit word. self - test operation: by selecting the control register bit (/slftst) self test o p- tion, the user may perform a functional test of the tran s- ceiver and support circuitry. the user can write data into the transmitter and it will be internally wrapped around into both receivers. the user can then verify reception and i n- tegrity of the data. the receiver line interface and the user's line drivers will not be tested. by setting the transmitter to use even parity, the user can test the receiver's parity circuit operation. power - up reset and master reset: the user must apply an active lo pulse to the master r e- set pin (/mr) after power up or upon system reset. prece d- ing the master reset at power - up an internal power - up reset occurs which will clear the transmitter such that no erron e- ous serial data stream will be transmitted before master reset. receivers, control register, and internal control logic are rese t by master reset. after resetting the device, the user must program the co n- trol register before beginning normal operation. the control register may be reprogrammed without additional reset pulses. proc essor interface: figure 7 shows a typical reset and initialization sequence. the user must pulse the /mr pin low to reset the de vice. to load the control register from the data bus, the /ldcw pin is pulsed low while the desired control data is applied on the data bus. figure 5 shows a typical transmitter loading sequence. it begins with the transmitter completing transmission of the previous data block. the txr flag goes hi to notify the user that data may be loaded into the buffer. the user sets entx to lo to disable the transmitter and proceeds to load a total of six arinc words into the buffer. (note that up to eight words could have been loaded). the user then enables the transmitter by setting entx to a logic "1" and the transmitter begins it's se quence of sending out data words. although not shown in the figure, the transmitter loading sequence can be interrupted by recei ver reading cycle with no interference between the two operations. figure 6 shows a typical receiver reading sequence. both receivers notify the user of valid data ready by setting their respective /drn lines to logic "0". the user responds by first r eading the two data words from receiver 1 and then from receiver 2. the sel line is normally a system a d- dress line and may assume any state, but must be valid when the /oen line is pulsed low.
page 8 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 transmitter ready (txr) enable transmitter (entx) load word 1 (/ld1) load word 2 (/ld2) data bus (d0 - d15) transmitter data (do(a)/do(b)) (w1) (w2) (w1) (w2) (w1) (w2) (w1) (w2) (w1) (w2) (w1) (w2) word 8 tx starts first word user enables tx user loads 6th word user loads 5th word user loads 4th word user loads 3rd word user loads 2nd word txr low indicates tx not empty user loads 1st word user disables tx txr high indicates tx is empty and user may load data txr transmitts last word from buffer word 1 figure 5: typical transmitter load sequence data ready 1 (/dr1) data ready 2 (/dr2) data enable 1 (/oe1) data enable 2 (/oe2) receiver select (sel) xxxxxxxxxxxxxxxx xxx xxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxx word 1 word 2 word 1 word 2 data bus (out) (d0 - d15) dr2 high indicates rx2 is empty user reads word 1 and word 2 from rx2 dr1 high indicates rx1 is empty user reads word 1 and word 2 from rx1 dr2 low indicates reception of valid data from rx2 dr1 low indicates rx1 is empty figure 6: typical receiver read sequence
page 9 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 valid data mr ldcw d0 - d15 t mr t pwld figure 7: reset and initialization sequence t hsel t doedr t oeoe t ddroe t pwoe t ssel arinc data bit 31 bit 32 word 1 valid word 2 valid t ddrn data ready flag (dr1 or dr2) data enable (oe1 or oe2) data word select (sel) data bus (d0 - d15) t ddr t dts don't care don't care don't care figure 8: receiver read operation and timing t dtxr t hdw t sdw t pwld word 1 valid word 2 valid load word 1 (/ld1) t ll load word 2 (/ld2) data bus (d0 - d15) transmitter ready (txr) figure 9: transmitter write operation and timing
page 10 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 t dtxr transmitter ready (txr) enable transmitter (entx) data out (do(a) or do(b)) transmitter clock (txck) t dtd t nul t bit t sktx t gap t dentx bit 1 bit 2 bit 32 bit 1 bit 32 . . . . . . . . . . . . . . . . . . . . . table 7: dei 1016 ac timing characteristics parameter symbol data rate 100kbps data rate 12.5kbps min max min max units write cycle timing /ld1, /ld2 and /ldcw pulse width t pwld 130 130 ns delay between consecutive load pulses t ll 0 0 ns data to /ld y set - up time t sdw 110 110 ns data to /ld y hold time t hdw 0 0 ns delay /ld2 y to txr ? t dtxr 840 840 ns read cycle timing delay, bit 32/25 in to /dr ? t ddrn 16 128 m s delay, /drn ? to /oen ? t ddroe 0 0 ns /oe1 or /oe2 pulse width t pwoe 200 200 ns delay between consecutive /oe pulses t oeoe 50 50 ns delay, 2nd /oe y to /drn y t doedr 200 200 ns sel to /oe ? to valid data t ssel 20 20 ns sel to /oe y hold time t hsel 20 20 ns delay /oe ? to valid data t ddr 200 200 ns sel to /oe y to data hi - z t dts 10 50 10 50 ns delay, entx y to output data 1 t dtd 25 200 m s output data null time t nul 4.95 5.05 39.6 40.4 m s output data bit time t bit 4.95 5.05 39.6 40.4 m s data skew between txck y ( ? ) and do y ( ? ) t sktx 0 50 0 50 ns data word gap time t gap 39.6 40.4 316.8 323.2 m s delay, end of tx word to txr y t dtxr 50 50 ns delay, txr y to entx ? t dentx 0 0 ns transmitter timing figure 10: transmitter timing diagram
page 11 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 s erial interface: the DEI1016 consits of two receive channels and one transmit channel. each receive channel operates ind e- pendently of each other and the transmitter. the r e- ceive data is asynchronous to the transmitter data and can also be at a different data rate than the transmitter. transmitter th e transmitter clock is free running and in phase with the transmitter data. the transmitter data (do(a) and do(b)) are ttl leve l signals. there are always at least 4 null bits between data words. an external arinc line driver is required to interface th e transmitter to the arinc serial data bus. see arinc 429 line dri v- ers below. receiver the receiver signals (di(a) and di(b)) are differential, bipolar, return - to - zero logic signals. the arinc cha n- nels can be connected directly to the receiver with no external components. arinc 429 line driver device engineering offers a co mplete line of arinc line drivers that support the arinc 429, 571, and 575 standards. please visit our website at http://www.de iaz. com to view and download data sheets for our line dri v- ers. 34 35 36 37 38 39 40 DEI1016 40 pin ceramic side brazed dip and DEI1016c 40 pin plastic dip 33 /ldcw n/c n/c 1mck txck /mr /dbcen 26 27 28 29 30 31 32 25 d1 d0 /ld1 /ld2 txr do(a) do(b) 24 23 d3 7 6 5 4 3 2 1 8 15 14 13 12 11 10 9 16 17 18 /dr2 /dr1 di2(b) di2(a) di1(b) di1(a) d4 d11 d12 d13 d14 d15 /oe2 /oe1 d9 19 20 v dd d7 22 21 d5 gnd sel d10 d8 d6 d2 entx 3 2 1 44 35 34 33 32 31 30 29 24 23 22 21 20 19 18 17 16 15 14 13 12 11 6 5 4 di1(b) di1(a) /dbcen di2(a) di2(b) gnd n/c n/c d10 d9 d8 d7 d6 do(b) do(a) d1 d0 /ld1 /oe1 d15 d14 d12 d11 /oe2 txr /ld2 d13 DEI1016b 44 - pin plastic plcc n/c n/c /ldcw entx v dd txck 1mck n/c 10 9 8 7 n/c /dr2 sel /dr1 28 27 26 25 d2 d5 d4 d3 39 38 37 36 43 42 41 40 /mr 41 40 39 38 29 28 27 26 25 24 23 18 17 16 15 14 13 12 11 10 9 8 7 6 5 44 43 42 di1(b) di1(a) /dbcen di2(a) di2(b) gnd n/c n/c d10 d9 d8 d7 d6 do(b) do(a) d1 d0 /ld1 /oe1 d15 d14 d12 d11 /oe2 txr /ld2 d13 DEI1016a 44 - pin plastic pqfp n/c n/c /ldcw entx v dd txck 1mck n/c 4 3 2 1 n/c /dr2 sel /dr1 22 21 20 19 d2 d5 d4 d3 33 32 31 30 37 36 35 34 /mr figure 11: DEI1016 and DEI1016c pin - out figure 12: DEI1016a pin - out figure 13: DEI1016b pin - out
page 12 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 cuag braze tungsten metallization plated kovar or alloy 42 lead aluminum bond wire kovar lid ausn solder seal die 0.100 typ .005 min 0.180 max 0.040 - 0.065 0.015 - .020 0.125 - .200 0.005 min 2.060 max 0.008 - .012 .590 - .615 .575 - .605 lead 1 id 1 1 1 n 2 notes 1. all dimensions in millimeters 2. dimensions shown in chart are nominal with tolerances as indicated a b d a a s d s a-b c m ddd 0.17 max. 6dp4 standoff 0.20 rad. typ. l a .25 b o 0.30 rad. typ. a 1 3. foot length "l" is measured at gage plane at 0.25 above the seating plane. a 1 10d typ. 10d typ. e basic p.25 p.25 p.10 p.10 max. o e d 1 1 a a 2 1 b e l e d a tols. leads dims. min./max. p.05 .25/.50 2.45 44l 10.00 10.00 .88 2.00 .80 .30 0d-7d 13.90 13.90 3.90 mm ddd .12 nom. ccc max. .10 c seating plane c ccc lead coplanarity +.10/-.05 +.15/-.10 footprint (body +) n 1 another variation of pin 1 visual aid e d d e 1 figure 14: DEI1016 40 pin ceramic side braze dip package dimensions figure 15: DEI1016a 44 lead 3.90mm pqfp package dimensions
page 13 of 13 ? device engineering inc. tempe, arizona DEI1016 rev. c july 20, 2000 pin 1 ident. .070 dia x .025 dp. .045 x 45 deg chamfer .045 x 45 deg corner chamfer .035 r .010 min .006 min 7 +/-2 deg 7 +/-2 deg typ .029 +/- .003 .017 +/- .004 notes : 1. all dimensions in inch. 2. surface finish : matte, charmille # 24-27 3. lead coplanarity after form to be within .004 another variation of castellation 30d 7d 7d 0.023/0.029 x 30d pkg. chamfer for rectangular pkg. for square pkg. .050 p .002 .030 p.005 .015 ref .020 min 0.654 0.152 0.010 0.654 0.690 0.690 figure 16: DEI1016b 44 lead plcc package dimensions 0 - 10 deg. .640 +/-.020 .610 +/-.010 .550 +/-.005 2.050 +/-.005 0.03 rad 0.020 min dimensions are in inches(mm) 0.100 typ .220 max .060 0.018 0.125 0.150 +/-.005 pin 1 figure 17: DEI1016c 40 pin plastic dip package dimensions

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